基于RISC-V的新型硬件性能计数器
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国家自然科学基金(61802402); 中国科学院率先行动“百人计划”青年俊才(C类)


Hardware Performance Counter Based on RISC-V
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    摘要:

    经过多年的发展, X86架构与ARM架构的处理器逐渐分别占据了桌面端和移动端市场的主导地位. 虽然无论从技术角度还是从生态体系方面, 这两类架构的处理器性能越来越高, 但是由于其指令集臃肿、技术复杂、授权困难等原因, 使得开发这两类架构的处理器的门槛较高. 研究院所还没有一个合适的指令集用于体系结构的研究和创新. RISC-V指令集的开源使得这一局面得以缓解. 其具备精简、开源、敏捷开发等特点引起了工业界与学术界的广泛关注与积极参与. 性能计数器(Hardware Performance Counter, HPC)是处理器研究和性能调优的重要工具. 由于RISC-V制定的标准性能计数器的可拓展性欠佳、可同时捕获事件的数量有限等不足, 本文提出一种新的基于RISC-V的分布式硬件性能计数器. 本文使用Genesys2开发板作为实验平台, 将这种性能计数器适配到lowRISC-v0.4开源SoC项目上, 完成了对该设计方案的验证与评估. 该性能计数器只占用3个控制状态寄存器(Control and Status Registers, CSRs)就可以同时捕获比标准的性能计数器多近乎一个数量级的事件, 在RISC-V处理器的性能分析、结构优化、侧信道攻防等方面为研究者提供了翔实的统计数据.

    Abstract:

    With decades of development, X86 and ARM have gradually dominated the markets of desktops and mobile phones. Although these two architectures are becoming increasingly powerful from the standing points of technical advances and software ecosystem, they are not good candidates for architectural research due to their complicated Instruction Set Architecture (ISA) definitions, comprehensive technical designs and intimidating copyright protection issues. Before the introduction of the open RISC-V ISA, there is no appropriate ISA for computer architectural research and innovation. RISC-V has attracted attention and participation from both the industry and academia. Hardware Performance Counter (HPC) is an important tool for researching and optimizing computer processor cores. The original definitions of HPC in the RISC-V standard do not scale properly and the number of events simultaneously monitorable is rather small. For these reasons, we propose a new distributed HPC based on RISC-V in this study. We have integrated this design into the lowRISC-v0.4 open SoC platform and run it on the Genesys2 FPGA board. Our HPC only uses three Control and Status Registers (CSRs) to capture all events. The number of events that can be concurrently monitored is one order of magnitude higher than that the RISC-V standard can support. Meanwhile, our strategy could provide detailed and accurate data for researchers focusing on the performance analysis of RISC-V processors, the architectural optimization, and side-channel attack and defense.

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薛子涵,解达,宋威.基于RISC-V的新型硬件性能计数器.计算机系统应用,2021,30(11):3-10

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  • 收稿日期:2021-04-27
  • 最后修改日期:2021-05-21
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  • 在线发布日期: 2021-10-22
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