A five stage pipeline CPU was designed and implemented on FPGA. Referring to MIPS machine and analyzing the process of each instruction, the process was divided into five stages which are IF, ID, EXE, MEM, and WB. The design of system-level structure was placed in the first position in order to determine the architecture and the instruction set. The next work was decomposing the integrated architecture and determining the signal connection between the module and the module. The CPU was implemented with VHDL. Finally, the five stage CPU was debugged by debugging software which is called Debug-controller. The result shows that the pipeline CPU is effective.