As an effective strategy to improve the efficiency for CPU reading and writing, and to fill the speed gap between CPU and the main memory, the cache in CPU makes the best of the locality theory by storing the latest or the most frequently used data. It dominates the performance of a CPU, and the microarchitecture of the cache, however, dominates the cache performance. The modern advanced cache commonly constructed with very complicated structures, contain multiple cache strategies, hardware algorithm and multi-level design, making it expensive to design and verify directly with hardware for time as well as money. Thus, it is far-reaching to simulate the hardware microarchitecture by software modeling. Cache microarchitecture simulator exactly assists the design or the evaluation of an excellent cache. In this article, a highly configurable and extensible cache microarchitecture functional simulator CMFSim is developed on the basis of hardware structure. It implements the common cache strategies and hardware algorithm, which can conveniently simulate the cache microarchitecture for the given configuration and analyze the performance with the specified parameters.