UVM-Based Universal Verification Platform for AMBA Bus Interface

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    According to the Moore’s Law, the scale of integrated circuits is getting bigger, and the integratable circuits within a single chip are increasingly complex. In a research and development cycle of an SoC chip, pre-layout verification becomes harder with more complex chip functions, taking uncontrollable time. How to reliably and efficiently verify complex chips within limited time represents a challenge to be addressed. In response to this problem, this paper customizes a UVM-based universal verification platform for AMBA bus interface. The platform is equipped with a scalable structure and random verification incentives, achieving dependable results. It can verify the modules to be tested in AMBA-APB, AMBA-AHB, and AMBA-AXI interfaces. In addition, the verification platform can be quickly set up for the target, and the preparation for pre-layout verification is simplified. The UVM-based platform produces random data with constraints, and verification results are converted into coverage reports, ensuring the efficiency and completeness.

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  • Received:November 10,2020
  • Revised:December 12,2020
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  • Online: July 02,2021
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