Optimization of RISC-V Vector Extension Stack Frame Layout Based on LLVM

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    For correct and optimized machine instructions, it is necessary to design and use a suitable program stack frame layout during the code generation stage of the compiler back-end. Due to the scalability of the RISC-V vector extension architecture and the unknown length of its vector register at compile time, the traditional stack frame layout cannot be applied. Although the previous stack frame layout implemented for vector extension in LLVM can generate correct machine instructions, it has problems such as many load/store instructions and reserved registers as well as large stack frame sizes. We analyze the problems existing in the previous implementation and propose a new layout and vector object calculation method on this basis. Then we verify it through the test set developed by the Barcelona Supercomputing Center. Experiments show that the new stack frame layout can greatly reduce the number of load/store instructions and stack space.

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  • Received:April 28,2021
  • Revised:May 21,2021
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  • Online: October 22,2021
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