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    2021,30(11):3-10, DOI: 10.15888/j.cnki.csa.008346
    Abstract:
    With decades of development, X86 and ARM have gradually dominated the markets of desktops and mobile phones. Although these two architectures are becoming increasingly powerful from the standing points of technical advances and software ecosystem, they are not good candidates for architectural research due to their complicated Instruction Set Architecture (ISA) definitions, comprehensive technical designs and intimidating copyright protection issues. Before the introduction of the open RISC-V ISA, there is no appropriate ISA for computer architectural research and innovation. RISC-V has attracted attention and participation from both the industry and academia. Hardware Performance Counter (HPC) is an important tool for researching and optimizing computer processor cores. The original definitions of HPC in the RISC-V standard do not scale properly and the number of events simultaneously monitorable is rather small. For these reasons, we propose a new distributed HPC based on RISC-V in this study. We have integrated this design into the lowRISC-v0.4 open SoC platform and run it on the Genesys2 FPGA board. Our HPC only uses three Control and Status Registers (CSRs) to capture all events. The number of events that can be concurrently monitored is one order of magnitude higher than that the RISC-V standard can support. Meanwhile, our strategy could provide detailed and accurate data for researchers focusing on the performance analysis of RISC-V processors, the architectural optimization, and side-channel attack and defense.
    2021,30(11):11-19, DOI: 10.15888/j.cnki.csa.008351
    Abstract:
    In computer systems, the memory overflow attack is a long-existing security problem and is still common nowadays, which can be effectively hindered by pointer encryption. Nevertheless, the implementation of the technique by software significantly lowers the program running efficiency and leads to additional memory overhead. In this study, we develop an encrypted/decrypted pointer coprocessor PEC-V based on the Rocket Custom Coprocessor (RoCC) interface of RocketChip. The overflow attack can be prevented through the control of encryption/decryption of the return address and function pointer by the coprocessor under the user-defined instruction of RISC-V. PEC-V mainly depends on Physical Unclonable Function (PUF) to avoid storing the key value of the encrypted pointer in memory. Thus, this mechanism not only ensures the randomness of the key value, but also reduces the times of accessing memory. The experimental results show that PEC-V is defensive against various buffer overflow attacks while the program running efficiency is only reduced by approximately 3% on average, which is better than previous mechanisms.
    2021,30(11):20-26, DOI: 10.15888/j.cnki.csa.008347
    Abstract:
    The RISC-V instruction set architecture features modularization and scalability. On the basis of the integer instruction set, the RISC-V architecture based processors can optionally support the official standard and non-standard custom instruction set extensions. This also means that, for each new custom extended instruction set, users need to implement corresponding support in the compiler toolchain. After analyzing the LLVM compilation framework and researching the general methods supporting RISC-V custom extended instructions, we conduct the implementation and verification with the XuanTie C910 custom instruction set as an example. The results can provide references for the research and implementation of RISC-V custom instruction set extension based on LLVM infrastructure.
    2021,30(11):27-32, DOI: 10.15888/j.cnki.csa.008349
    Abstract:
    For correct and optimized machine instructions, it is necessary to design and use a suitable program stack frame layout during the code generation stage of the compiler back-end. Due to the scalability of the RISC-V vector extension architecture and the unknown length of its vector register at compile time, the traditional stack frame layout cannot be applied. Although the previous stack frame layout implemented for vector extension in LLVM can generate correct machine instructions, it has problems such as many load/store instructions and reserved registers as well as large stack frame sizes. We analyze the problems existing in the previous implementation and propose a new layout and vector object calculation method on this basis. Then we verify it through the test set developed by the Barcelona Supercomputing Center. Experiments show that the new stack frame layout can greatly reduce the number of load/store instructions and stack space.
    2021,30(11):33-40, DOI: 10.15888/j.cnki.csa.008348
    Abstract:
    In this study, we design and implement an automatic testing system for semantic equivalence of RISC-V assembly programs. While developing RISC-V programs, especially developing efficient programs based on extension instructions (such as vector extension), developers often write assembly code manually. For example, for the standard C function library, we often write the corresponding vector version functions for better performance. Without the compiler, the manually developed assembly code can maximize the efficiency of the program, but it skips many important compilation processes (such as type checking and register allocation), thus putting forward higher requirements for the developers. It will greatly affect the correctness of the code and the efficiency of software development and debugging if we can quickly and automatically test whether the rewritten version is semantically equivalent to the standard version of the program. The existing RISC-V testing framework lacks support for semantic equivalence testing and fails to consider the side effects caused by program executions. Based on the dynamic test environment of a simulator, this research designs and implements an automatic testing system for semantic equivalence of RISC-V assembly programs. It can capture side effects caused by program executions through monitoring machine states and generate testing reports with user-defined testing targets. Experiments show that the system, compared with existing testing systems, can test the semantic equivalence of RISC-V assembly programs.
    2021,30(11):41-45, DOI: 10.15888/j.cnki.csa.008350
    Abstract:
    This study introduces the hardware connection scheme for an embedded intelligent car control system based on RISC-V, the state analysis method of an intelligent car based on a state machine, and the motor control scheme in different application scenarios. The system takes the FPGA development board running the RISC-V softcore as the main control board of the intelligent car and collects the signals from the ultrasonic sensor and infrared sensor of the intelligent car through the GPIO module of RISC-V to detect the obstacles in front and rear of the car respectively. Moreover, it uses the GPIO interrupt to respond quickly to the signals from the collision detection sensor and tilt angle sensor and adopts the PWM module for the motor control in different scenarios. The test results show that the control system introduced in this paper can fulfill the functions of the intelligent car, such as autonomous obstacle avoidance, collision detection, and attitude detection.
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    Available online:  October 19, 2021 , DOI: 10.15888/j.cnki.csa.008467
    Abstract:
    Leaf vein segmentation is an important step in leaf pattern analysis, which is of great significance for soybean variety identification and phenotype research. On account of the complicated leaf texture of soybean and the low contrast of the leaf area where the veins are located, it is generally impossible to achieve ideal segmentation results only by using gray information to segment leaf vein. This paper presents a means of soybean vein segmentation combining multi-scale gray unconstrained hit-or-miss transform (UHMT) algorithm and the processing method based on the hue data of HSI color space. In this means, the gray information in RGB color space and the hue data in HSI color space are used to segment the global leaf veins and local primary and secondary veins from soybean leaf image separately. The former uses iterative threshold segmentation to extract the leaf area, and eliminates interference factors such as the outer contour and the petiole of the leaf through expansion and corrosion, and obtains the leaf area image. Then, the multi-scale gray UHMT algorithm is used to obtain the global leaf vein image. Contraposing the matter of poor segmentation effect of primary and secondary veins, the latter uses hue data to enlarge the discrepancies in gray value between veins pixels and other pixels to realize the segmentation of local primary and secondary veins. The obtained global and local vein images are fused into the final soybean leaf vein image. This paper uses soybean leaf images in the soybean leaf image database, SoyCultivar, to verify the effectiveness of the algorithm. The results indicate that this algorithm is better than the existing leaf vein segmentation methods, not only can extract soybean leaf veins completely, but also can well eliminate the background, leaf contours, petiole and other irrelevant components.
    Available online:  July 13, 2021 , DOI: 10.15888/j.cnki.csa.008280
    Abstract:
    With the continuous development of digital twin technology at this stage, research and applications surrounding digital twins have gradually become a hot spot. Because traditional automated driving test methods have various defects in terms of functionality, safety, and test cost, this article proposes a digital twin automatic driving test method based on the basic characteristics of the digital twin and the test method of autonomous driving. The method of constructing the driving test environment uses spatial coordinate mapping, collision detection model, and virtual scene registration to map the automatic driving information in the actual environment to the virtual scene. At the same time, the corresponding mixed reality automatic driving test model is constructed and passed the experiment. The collision test with interactive features of the mixed reality system is shown. The performance of the system at sampling frequencies of 50ms, 200ms and 1000ms is compared and analyzed. Experiments show that the algorithm in this paper has better operating frame rate characteristics at the sampling frequency of 200ms or above.
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    2000,9(2):38-41, DOI:
    [Abstract] (11381) [HTML] (0) [PDF ] (9385)
    Abstract:
    本文详细讨论了VRML技术与其他数据访问技术相结合 ,实现对数据库实时交互的技术实现方法 ,并简要阐述了相关技术规范的语法结构和技术要求。所用技术手段安全可靠 ,具有良好的实际应用表现 ,便于系统移植。
    1993,2(8):41-42, DOI:
    [Abstract] (8099) [HTML] (0) [PDF ] (9754)
    Abstract:
    本文介绍了作者近年来应用工具软件NU清除磁盘引导区和硬盘主引导区病毒、修复引导区损坏磁盘的 经验,经实践检验,简便有效。
    1995,4(5):2-5, DOI:
    [Abstract] (7795) [HTML] (0) [PDF ] (6835)
    Abstract:
    本文简要介绍了海关EDI自动化通关系统的定义概况及重要意义,对该EDI应用系统下的业务运作模式所涉及的法律问题,采用EDIFACT国际标准问题、网络与软件技术问题,以及工程管理问题进行了结合实际的分析。
    2011,20(11):80-85, DOI:
    [Abstract] (6635) [HTML] () [PDF 863160] (16455)
    Abstract:
    在研究了目前主流的视频转码方案基础上,提出了一种分布式转码系统。系统采用HDFS(HadoopDistributed File System)进行视频存储,利用MapReduce 思想和FFMPEG 进行分布式转码。详细讨论了视频分布式存储时的分段策略,以及分段大小对存取时间的影响。同时,定义了视频存储和转换的元数据格式。提出了基于MapReduce 编程框架的分布式转码方案,即Mapper 端进行转码和Reducer 端进行视频合并。实验数据显示了转码时间随视频分段大小和转码机器数量不同而变化的趋势。结
    2008,17(5):122-126, DOI:
    [Abstract] (6317) [HTML] (0) [PDF ] (21851)
    Abstract:
    随着Internet的迅速发展,网络资源越来越丰富,人们如何从网络上抽取信息也变得至关重要,尤其是占网络资源80%的Deep Web信息检索更是人们应该倍加关注的难点问题。为了更好的研究Deep Web爬虫技术,本文对有关Deep Web爬虫的内容进行了全面、详细地介绍。首先对Deep Web爬虫的定义及研究目标进行了阐述,接着介绍了近年来国内外关于Deep Web爬虫的研究进展,并对其加以分析。在此基础上展望了Deep Web爬虫的研究趋势,为下一步的研究奠定了基础。
    2016,25(8):1-7, DOI: 10.15888/j.cnki.csa.005283
    [Abstract] (6119) [HTML] () [PDF 1167952] (19253)
    Abstract:
    从2006年开始,深度神经网络在图像/语音识别、自动驾驶等大数据处理和人工智能领域中都取得了巨大成功,其中无监督学习方法作为深度神经网络中的预训练方法为深度神经网络的成功起到了非常重要的作用. 为此,对深度学习中的无监督学习方法进行了介绍和分析,主要总结了两类常用的无监督学习方法,即确定型的自编码方法和基于概率型受限玻尔兹曼机的对比散度等学习方法,并介绍了这两类方法在深度学习系统中的应用,最后对无监督学习面临的问题和挑战进行了总结和展望.
    1999,8(7):43-46, DOI:
    [Abstract] (5984) [HTML] (0) [PDF ] (8964)
    Abstract:
    用较少的颜色来表示较大的色彩空间一直是人们研究的课题,本文详细讨论了半色调技术和抖动技术,并将它们扩展到实用的真彩色空间来讨论,并给出了实现的算法。
    2007,16(9):22-25, DOI:
    [Abstract] (5736) [HTML] (0) [PDF ] (2347)
    Abstract:
    本文结合物流遗留系统的实际安全状态,分析了面向对象的编程思想在横切关注点和核心关注点处理上的不足,指出面向方面的编程思想解决方案对系统进行分离关注点处理的优势,并对面向方面的编程的一种具体实现AspectJ进行分析,提出了一种依据AspectJ对遗留物流系统进行IC卡安全进化的方法.
    2012,21(3):260-264, DOI:
    [Abstract] (4981) [HTML] () [PDF 336300] (18632)
    Abstract:
    开放平台的核心问题是用户验证和授权问题,OAuth 是目前国际通用的授权方式,它的特点是不需要用户在第三方应用输入用户名及密码,就可以申请访问该用户的受保护资源。OAuth 最新版本是OAuth2.0,其认证与授权的流程更简单、更安全。研究了OAuth2.0 的工作原理,分析了刷新访问令牌的工作流程,并给出了OAuth2.0 服务器端的设计方案和具体的应用实例。
    2011,20(7):184-187,120, DOI:
    [Abstract] (4965) [HTML] () [PDF 731903] (20230)
    Abstract:
    针对智能家居、环境监测等的实际要求,设计了一种远距离通讯的无线传感器节点。该系统采用集射频与控制器于一体的第二代片上系统CC2530 为核心模块,外接CC2591 射频前端功放模块;软件上基于ZigBee2006 协议栈,在ZStack 通用模块基础上实现应用层各项功能。介绍了基于ZigBee 协议构建无线数据采集网络,给出了传感器节点、协调器节点的硬件设计原理图及软件流程图。实验证明节点性能良好、通讯可靠,通讯距离较TI 第一代产品有明显增大。
    2004,13(10):7-9, DOI:
    [Abstract] (4935) [HTML] (0) [PDF ] (6069)
    Abstract:
    本文介绍了车辆监控系统的组成,研究了如何应用Rockwell GPS OEM板和WISMOQUIKQ2406B模块进行移动单元的软硬件设计,以及监控中心 GIS软件的设计.重点介绍嵌入TCP/IP协议处理的Q2406B模块如何通过AT指令接入Internet以及如何和监控中心传输TCP数据.
    2008,17(8):87-89, DOI:
    [Abstract] (4880) [HTML] (0) [PDF ] (20512)
    Abstract:
    随着面向对象软件开发技术的广泛应用和软件测试自动化的要求,基于模型的软件测试逐渐得到了软件开发人员和软件测试人员的认可和接受。基于模型的软件测试是软件编码阶段的主要测试方法之一,具有测试效率高、排除逻辑复杂故障测试效果好等特点。但是误报、漏报和故障机理有待进一步研究。对主要的测试模型进行了分析和分类,同时,对故障密度等参数进行了初步的分析;最后,提出了一种基于模型的软件测试流程。
    2008,17(8):2-5, DOI:
    [Abstract] (4864) [HTML] (0) [PDF ] (11953)
    Abstract:
    本文介绍了一个企业信息门户中单点登录系统的设计与实现。系统实现了一个基于Java EE架构的结合凭证加密和Web Services的单点登录系统,对门户用户进行统一认证和访问控制。论文详细阐述了该系统的总体结构、设计思想、工作原理和具体实现方案,目前系统已在部分省市的广电行业信息门户平台中得到了良好的应用。
    2008,17(1):113-116, DOI:
    [Abstract] (4819) [HTML] (0) [PDF ] (26008)
    Abstract:
    排序是计算机程序设计中一种重要操作,本文论述了C语言中快速排序算法的改进,即快速排序与直接插入排序算法相结合的实现过程。在C语言程序设计中,实现大量的内部排序应用时,所寻求的目的就是找到一个简单、有效、快捷的算法。本文着重阐述快速排序的改进与提高过程,从基本的性能特征到基本的算法改进,通过不断的分析,实验,最后得出最佳的改进算法。
    2010,19(10):42-46, DOI:
    [Abstract] (4766) [HTML] () [PDF 1301305] (10541)
    Abstract:
    综合考虑基于构件组装技术的虚拟实验室的系统需求,分析了工作流驱动的动态虚拟实验室的业务处理模型,介绍了轻量级J2EE框架(SSH)与工作流系统(Shark和JaWE)的集成模型,提出了一种轻量级J2EE框架下工作流驱动的动态虚拟实验室的设计和实现方法,给出了虚拟实验项目的实现机制、数据流和控制流的管理方法,以及实验流程的动态组装方法,最后,以应用实例说明了本文方法的有效性。
    2004,13(8):58-59, DOI:
    [Abstract] (4735) [HTML] (0) [PDF ] (8859)
    Abstract:
    本文介绍了Visual C++6.0在对话框的多个文本框之间,通过回车键转移焦点的几种方法,并提出了一个改进方法.
    2009,18(5):182-185, DOI:
    [Abstract] (4701) [HTML] (0) [PDF ] (15860)
    Abstract:
    DICOM 是医学图像存储和传输的国际标准,DCMTK 是免费开源的针对DICOM 标准的开发包。解读DICOM 文件格式并解决DICOM 医学图像显示问题是医学图像处理的基础,对医学影像技术的研究具有重要意义。解读了DICOM 文件格式并介绍了调窗处理的原理,利用VC++和DCMTK 实现医学图像显示和调窗功能。
    2009,18(3):164-167, DOI:
    [Abstract] (4660) [HTML] (0) [PDF ] (18195)
    Abstract:
    介绍了一种基于DWGDirectX在不依赖于AutoCAD平台的情况下实现DWG文件的显示、操作、添加的简单的实体的方法,并对该方法进行了分析和实现。
    2003,12(1):62-65, DOI:
    [Abstract] (4586) [HTML] (0) [PDF ] (8293)
    Abstract:
    本文介绍了一种将DTD转换成ER图,并用XMLApplication将ER图描述成转换标准,然后根据该转换标准将XML文档转换为关系模型的方法.
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    2007,16(10):48-51, DOI:
    [Abstract] (3817) [HTML] (0) [PDF 0.00 Byte] (75418)
    Abstract:
    论文对HDF数据格式和函数库进行研究,重点以栅格图像为例,详细论述如何利用VC++.net和VC#.net对光栅数据进行读取与处理,然后根据所得到的象素矩阵用描点法显示图像.论文是以国家气象中心开发Micaps3.0(气象信息综合分析处理系统)的课题研究为背景的.
    2002,11(12):67-68, DOI:
    [Abstract] (2498) [HTML] (0) [PDF 0.00 Byte] (31727)
    Abstract:
    本文介绍非实时操作系统Windows 2000下,利用VisualC++6.0开发实时数据采集的方法.所用到的数据采集卡是研华的PCL-818L.借助数据采集卡PCL-818L的DLLs中的API函数,提出三种实现高速实时数据采集的方法及优缺点.
    2008,17(1):113-116, DOI:
    [Abstract] (4819) [HTML] (0) [PDF 0.00 Byte] (26008)
    Abstract:
    排序是计算机程序设计中一种重要操作,本文论述了C语言中快速排序算法的改进,即快速排序与直接插入排序算法相结合的实现过程。在C语言程序设计中,实现大量的内部排序应用时,所寻求的目的就是找到一个简单、有效、快捷的算法。本文着重阐述快速排序的改进与提高过程,从基本的性能特征到基本的算法改进,通过不断的分析,实验,最后得出最佳的改进算法。
    2008,17(5):122-126, DOI:
    [Abstract] (6317) [HTML] (0) [PDF 0.00 Byte] (21851)
    Abstract:
    随着Internet的迅速发展,网络资源越来越丰富,人们如何从网络上抽取信息也变得至关重要,尤其是占网络资源80%的Deep Web信息检索更是人们应该倍加关注的难点问题。为了更好的研究Deep Web爬虫技术,本文对有关Deep Web爬虫的内容进行了全面、详细地介绍。首先对Deep Web爬虫的定义及研究目标进行了阐述,接着介绍了近年来国内外关于Deep Web爬虫的研究进展,并对其加以分析。在此基础上展望了Deep Web爬虫的研究趋势,为下一步的研究奠定了基础。

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