Abstract: With decades of development, X86 and ARM have gradually dominated the markets of desktops and mobile phones. Although these two architectures are becoming increasingly powerful from the standing points of technical advances and software ecosystem, they are not good candidates for architectural research due to their complicated Instruction Set Architecture (ISA) definitions, comprehensive technical designs and intimidating copyright protection issues. Before the introduction of the open RISC-V ISA, there is no appropriate ISA for computer architectural research and innovation. RISC-V has attracted attention and participation from both the industry and academia. Hardware Performance Counter (HPC) is an important tool for researching and optimizing computer processor cores. The original definitions of HPC in the RISC-V standard do not scale properly and the number of events simultaneously monitorable is rather small. For these reasons, we propose a new distributed HPC based on RISC-V in this study. We have integrated this design into the lowRISC-v0.4 open SoC platform and run it on the Genesys2 FPGA board. Our HPC only uses three Control and Status Registers (CSRs) to capture all events. The number of events that can be concurrently monitored is one order of magnitude higher than that the RISC-V standard can support. Meanwhile, our strategy could provide detailed and accurate data for researchers focusing on the performance analysis of RISC-V processors, the architectural optimization, and side-channel attack and defense.
Abstract: In computer systems, the memory overflow attack is a long-existing security problem and is still common nowadays, which can be effectively hindered by pointer encryption. Nevertheless, the implementation of the technique by software significantly lowers the program running efficiency and leads to additional memory overhead. In this study, we develop an encrypted/decrypted pointer coprocessor PEC-V based on the Rocket Custom Coprocessor (RoCC) interface of RocketChip. The overflow attack can be prevented through the control of encryption/decryption of the return address and function pointer by the coprocessor under the user-defined instruction of RISC-V. PEC-V mainly depends on Physical Unclonable Function (PUF) to avoid storing the key value of the encrypted pointer in memory. Thus, this mechanism not only ensures the randomness of the key value, but also reduces the times of accessing memory. The experimental results show that PEC-V is defensive against various buffer overflow attacks while the program running efficiency is only reduced by approximately 3% on average, which is better than previous mechanisms.
Abstract: The RISC-V instruction set architecture features modularization and scalability. On the basis of the integer instruction set, the RISC-V architecture based processors can optionally support the official standard and non-standard custom instruction set extensions. This also means that, for each new custom extended instruction set, users need to implement corresponding support in the compiler toolchain. After analyzing the LLVM compilation framework and researching the general methods supporting RISC-V custom extended instructions, we conduct the implementation and verification with the XuanTie C910 custom instruction set as an example. The results can provide references for the research and implementation of RISC-V custom instruction set extension based on LLVM infrastructure.
Abstract: For correct and optimized machine instructions, it is necessary to design and use a suitable program stack frame layout during the code generation stage of the compiler back-end. Due to the scalability of the RISC-V vector extension architecture and the unknown length of its vector register at compile time, the traditional stack frame layout cannot be applied. Although the previous stack frame layout implemented for vector extension in LLVM can generate correct machine instructions, it has problems such as many load/store instructions and reserved registers as well as large stack frame sizes. We analyze the problems existing in the previous implementation and propose a new layout and vector object calculation method on this basis. Then we verify it through the test set developed by the Barcelona Supercomputing Center. Experiments show that the new stack frame layout can greatly reduce the number of load/store instructions and stack space.
Abstract: In this study, we design and implement an automatic testing system for semantic equivalence of RISC-V assembly programs. While developing RISC-V programs, especially developing efficient programs based on extension instructions (such as vector extension), developers often write assembly code manually. For example, for the standard C function library, we often write the corresponding vector version functions for better performance. Without the compiler, the manually developed assembly code can maximize the efficiency of the program, but it skips many important compilation processes (such as type checking and register allocation), thus putting forward higher requirements for the developers. It will greatly affect the correctness of the code and the efficiency of software development and debugging if we can quickly and automatically test whether the rewritten version is semantically equivalent to the standard version of the program. The existing RISC-V testing framework lacks support for semantic equivalence testing and fails to consider the side effects caused by program executions. Based on the dynamic test environment of a simulator, this research designs and implements an automatic testing system for semantic equivalence of RISC-V assembly programs. It can capture side effects caused by program executions through monitoring machine states and generate testing reports with user-defined testing targets. Experiments show that the system, compared with existing testing systems, can test the semantic equivalence of RISC-V assembly programs.
Abstract: This study introduces the hardware connection scheme for an embedded intelligent car control system based on RISC-V, the state analysis method of an intelligent car based on a state machine, and the motor control scheme in different application scenarios. The system takes the FPGA development board running the RISC-V softcore as the main control board of the intelligent car and collects the signals from the ultrasonic sensor and infrared sensor of the intelligent car through the GPIO module of RISC-V to detect the obstacles in front and rear of the car respectively. Moreover, it uses the GPIO interrupt to respond quickly to the signals from the collision detection sensor and tilt angle sensor and adopts the PWM module for the motor control in different scenarios. The test results show that the control system introduced in this paper can fulfill the functions of the intelligent car, such as autonomous obstacle avoidance, collision detection, and attitude detection.
Abstract: Leaf vein segmentation is an important step in leaf pattern analysis, which is of great significance for soybean variety identification and phenotype research. On account of the complicated leaf texture of soybean and the low contrast of the leaf area where the veins are located, it is generally impossible to achieve ideal segmentation results only by using gray information to segment leaf vein. This paper presents a means of soybean vein segmentation combining multi-scale gray unconstrained hit-or-miss transform (UHMT) algorithm and the processing method based on the hue data of HSI color space. In this means, the gray information in RGB color space and the hue data in HSI color space are used to segment the global leaf veins and local primary and secondary veins from soybean leaf image separately. The former uses iterative threshold segmentation to extract the leaf area, and eliminates interference factors such as the outer contour and the petiole of the leaf through expansion and corrosion, and obtains the leaf area image. Then, the multi-scale gray UHMT algorithm is used to obtain the global leaf vein image. Contraposing the matter of poor segmentation effect of primary and secondary veins, the latter uses hue data to enlarge the discrepancies in gray value between veins pixels and other pixels to realize the segmentation of local primary and secondary veins. The obtained global and local vein images are fused into the final soybean leaf vein image. This paper uses soybean leaf images in the soybean leaf image database, SoyCultivar, to verify the effectiveness of the algorithm. The results indicate that this algorithm is better than the existing leaf vein segmentation methods, not only can extract soybean leaf veins completely, but also can well eliminate the background, leaf contours, petiole and other irrelevant components.
Abstract: With the continuous development of digital twin technology at this stage, research and applications surrounding digital twins have gradually become a hot spot. Because traditional automated driving test methods have various defects in terms of functionality, safety, and test cost, this article proposes a digital twin automatic driving test method based on the basic characteristics of the digital twin and the test method of autonomous driving. The method of constructing the driving test environment uses spatial coordinate mapping, collision detection model, and virtual scene registration to map the automatic driving information in the actual environment to the virtual scene. At the same time, the corresponding mixed reality automatic driving test model is constructed and passed the experiment. The collision test with interactive features of the mixed reality system is shown. The performance of the system at sampling frequencies of 50ms, 200ms and 1000ms is compared and analyzed. Experiments show that the algorithm in this paper has better operating frame rate characteristics at the sampling frequency of 200ms or above.
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